In the modern era, where meeting high performance and low power targets for any complex SoC (System on Chip) is very tough, testing the SoC has become even more challenging. The purpose of several DFT ...

SLE has introduced a scan insertion tool – ScanBlaster is designed to take physical effects into account very early, and to be compatible with many standard test insertion methodologies. The tool can ...

In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram ...

In deep sub-micron technology nodes (180nm and lower), the design process of SoC becomes complex by integrating multiple IPs having different functionalities on a single chip. In such a scenario, ...

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...

Mentor Graphics has developed a compression system for scan chain testing of semiconductors that can reduce test data and test time by a factor of ten. Instead of feeding test vectors direct to 16 ...

Santa Cruz, Calif. — Think your "smart" credit cards are safe from hackers, that your company firewall is secure and that no one can steal the intellectual property in your latest chip design? Think ...

Design automation is the key to the development of very large ICs. Optimizing the connection and layout of millions of gates to efficiently perform complex functions is not a job to which humans are ...